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wireless power transmitter for 15w applications p9242 - r datasheet ? 2016 integrated device technology, inc 1 december 16, 2016 description the p9242 - r is a highly integrated , magnetic induction , wireless power transmitter supporting up to 15w . the system - on - chip operates with an input voltage range of 4.25 v to 21v . the transmitter includes an industry - leading 32 - bit arm? cortex? - m0 processor offering a high level of programmability while consuming extremely low standby power. the p9242 - r features two led outputs with pre - defined user - programmable blinking patt erns, buzzer , and programmable over - current protection supporting a wide range of applications. the i 2 c serial commun ication allows the user to read information such as voltage, current, frequency , and fault conditions . the p9242 - r includes an under - voltag e lockout and thermal management cir - cuit to safe guard the device under fault co nditions. together with the p9221 - r receiver (r x ) , the p9242 - r is a complete wireless power system solution. the p9242 - r is available in a lead - free, space - saving 48 - vfqfn package . the product is rated for a - 40oc to +85oc operating temperature range . typical applications ? charging pad ? accessories ? cradle ? t ablets feature s ? power transfer u p to 15 w ? wide input voltage range: 4.25 v to 21v ? wpc - 1.2.2 compliant , mp - a2 coil configuration ? integrated s tep - down s witching r egulator ? embedded 32 - bit arm? cortex? - m0 processor ? integrated drivers for external power fets ? simultaneous voltage and current demodulation scheme for communication ? integrated current sense amplifier ? low standby power ? dedicated remote temperature sensing ? programmable current limit ? power transfer led indicator ? f oreign objects detection (fod) ? pre - define d user - programmable led pattern ? active - low enable pin for electrical on/off ? over - current and over - temperature protection ? supports i 2 c interface ? - 4 0 to +85c ambient operating temperature range ? 48 - vfqfn ( 6 ? 6 mm ) rohs - compliant package basic application circuit 1 2 v c s p c s n v i n p e a k d e t e c t o r v d e m 1 c o i l a s s e m b l y p 9 2 4 2 - r s w _ s l d o 3 3 l d o 1 8 p r e g g n d l e d 1 l e d 2 v i n _ l d o r s n s p r o g r a m m i n g r e s i s t o r s g h _ b r g 1 s w _ b r g 1 g l _ b r g 1 g h _ b r g 2 s w _ b r g 2 g l _ b r g 2 i l i m l e d _ p a t l p c p l
p9242 - r datasheet ? 2016 integrated device technology, inc 2 december 16, 2016 contents 1. pin assignments ................................ ................................ ................................ ................................ ................................ ........................... 5 2. pin descriptions ................................ ................................ ................................ ................................ ................................ ............................ 6 3. absolute maximum ratings ................................ ................................ ................................ ................................ ................................ .......... 8 4. electrical characteristics ................................ ................................ ................................ ................................ ................................ .............. 9 5. typical performance characteristics ................................ ................................ ................................ ................................ .......................... 11 6. function block diagram ................................ ................................ ................................ ................................ ................................ ............. 13 7. theory of operation ................................ ................................ ................................ ................................ ................................ .................... 14 7.1 over - current limit C ilim ................................ ................................ ................................ ................................ ................................ .. 14 7.2 enable pin C en ................................ ................................ ................................ ................................ ................................ ................ 14 7.3 buzzer C buzr ................................ ................................ ................................ ................................ ................................ .................. 14 7.4 voltage demodulation C vdem1 ................................ ................................ ................................ ................................ ....................... 14 7.5 current demodulation C idemi ................................ ................................ ................................ ................................ ......................... 15 7.6 thermal protection ................................ ................................ ................................ ................................ ................................ ............ 15 7.7 external temperature sensing C ts ................................ ................................ ................................ ................................ ................. 15 7.8 leds pattern selection C led_pat ................................ ................................ ................................ ................................ ................. 15 7.9 foreign object detection ................................ ................................ ................................ ................................ ................................ ... 16 7.10 step - down regulator ................................ ................................ ................................ ................................ ................................ ........ 17 7.11 linear regulators C preg, ldo33, and ldo18 ................................ ................................ ................................ .............................. 17 7.12 under - voltage lock - out (uvlo) protection ................................ ................................ ................................ ................................ ...... 17 7.13 lc resonant circuit ................................ ................................ ................................ ................................ ................................ .......... 17 8. commu nication interface ................................ ................................ ................................ ................................ ................................ ............ 18 8.1 modulation/communication ................................ ................................ ................................ ................................ ............................... 18 8.2 bit decoding scheme for ask ................................ ................................ ................................ ................................ ........................... 19 8.3 byte decoding for ask ................................ ................................ ................................ ................................ ................................ ...... 19 8.4 packet structure ................................ ................................ ................................ ................................ ................................ ................ 1 9 9. wpc mode characteristics ................................ ................................ ................................ ................................ ................................ ........ 20 9.1 selection phase ................................ ................................ ................................ ................................ ................................ ................. 20 9.2 ping phase (digital ping) ................................ ................................ ................................ ................................ ................................ ... 20 9.3 identification and configuration phase ................................ ................................ ................................ ................................ .............. 21 9.4 negotiation phase ................................ ................................ ................................ ................................ ................................ ............. 21 9.5 calibration phase ................................ ................................ ................................ ................................ ................................ .............. 21 9. 6 power transfer phase ................................ ................................ ................................ ................................ ................................ ....... 21 10. functional registers ................................ ................................ ................................ ................................ ................................ ................... 22 11. application information ................................ ................................ ................................ ................................ ................................ ............... 24 11.1 power dissipation and thermal requirements ................................ ................................ ................................ ................................ . 24 11.2 typical application schematic ................................ ................................ ................................ ................................ ........................... 25 11.3 bill of materials (bom) ................................ ................................ ................................ ................................ ................................ ....... 26 12. package outline drawing ................................ ................................ ................................ ................................ ................................ ........... 28
p9242 - r datasheet ? 2016 integrated device technology, inc 3 december 16, 2016 13. recommended land pattern ................................ ................................ ................................ ................................ ................................ ...... 29 14. special notes: ndg 48 - vfqfn package assembly ................................ ................................ ................................ ................................ .. 30 15. marking diagram ................................ ................................ ................................ ................................ ................................ ........................ 30 16. ordering information ................................ ................................ ................................ ................................ ................................ ................... 30 17. revision history ................................ ................................ ................................ ................................ ................................ .......................... 31 list of figures figure 1. pin assignments ................................ ................................ ................................ ................................ ................................ .................. 5 figure 2. efficiency vs. output load: v out_rx = 12v ................................ ................................ ................................ ................................ ......... 11 figure 3. efficiency vs. output load: v out_rx = 9v ................................ ................................ ................................ ................................ ........... 11 figure 4. efficiency vs. output load: v out_rx = 5v ................................ ................................ ................................ ................................ ........... 11 figure 5. load regulation vs. output load: vcc_5v in schematic figure 24 ................................ ................................ ................................ . 11 figure 6. load regulation vs. output load: ldo33 ................................ ................................ ................................ ................................ ......... 11 figure 7. load regulation vs. outp ut load: ldo18 ................................ ................................ ................................ ................................ ......... 11 figure 8. over - current limit vs. v ilim ................................ ................................ ................................ ................................ ............................... 12 figure 9. voltage and current signal for demodulation ................................ ................................ ................................ ................................ ... 12 figure 10. enable startup ................................ ................................ ................................ ................................ ................................ ................... 12 fi gure 11. communication packet during r x load step from 0 to 1.3a ................................ ................................ ................................ ............ 12 figure 12. communication packet during r x load step from 1. 3a to 0 ................................ ................................ ................................ ............ 12 figure 13. functional block diagram ................................ ................................ ................................ ................................ ................................ .. 13 figure 14. voltage mode envelope detector ................................ ................................ ................................ ................................ ...................... 14 figure 15. current mode envelope detector ................................ ................................ ................................ ................................ ...................... 15 figure 16. ntc thermistor connection to ts pin ................................ ................................ ................................ ................................ .............. 15 figure 17. uvlo threshold definition ................................ ................................ ................................ ................................ ................................ 17 figure 18. example of differential bi - phase encoding for fsk ................................ ................................ ................................ .......................... 18 figure 19. example of asynchronous serial byte format for fsk ................................ ................................ ................................ ..................... 18 figure 20. bit decoding scheme ................................ ................................ ................................ ................................ ................................ ........ 19 figure 21. byte decoding scheme ................................ ................................ ................................ ................................ ................................ ..... 19 figure 22. communication packet structure ................................ ................................ ................................ ................................ ...................... 19 figure 23. wpc power transfer phases flow chart ................................ ................................ ................................ ................................ ......... 20 figure 24. p9242 - r typical application schematic ................................ ................................ ................................ ................................ ............ 25 figure 25. 48 - vfqfn package outline drawing ................................ ................................ ................................ ................................ ................ 28 figure 26. 48 - vfqfn land pattern drawing ................................ ................................ ................................ ................................ ..................... 29
p9242 - r datasheet ? 2016 integrated device technology, inc 4 december 16, 2016 list of tables table 1. pin descriptions ................................ ................................ ................................ ................................ ................................ ................... 6 table 2. absolute maximum ratings ................................ ................................ ................................ ................................ ................................ . 8 table 3. package thermal information ................................ ................................ ................................ ................................ ............................. 8 table 4. esd information ................................ ................................ ................................ ................................ ................................ .................. 8 table 5. electrical characteristics ................................ ................................ ................................ ................................ ................................ ..... 9 table 6. led pattern selection ................................ ................................ ................................ ................................ ................................ ....... 16 table 7. state register ................................ ................................ ................................ ................................ ................................ .................... 22 table 8. status register ................................ ................................ ................................ ................................ ................................ .................. 22 table 9. read register C coil current ................................ ................................ ................................ ................................ ............................ 22 table 10. read register C coil voltage ................................ ................................ ................................ ................................ ............................ 23 table 11. read register C remote temperature sensing voltage ................................ ................................ ................................ .................. 23 table 12. read register C operating frequency ................................ ................................ ................................ ................................ .............. 23 table 13. read register C operating duty cycle ................................ ................................ ................................ ................................ .............. 23 table 14. read register C full/half bridge statu s ................................ ................................ ................................ ................................ ............ 23 table 15. p9242 - r mm evaluation kit v2.1 bill of materials ................................ ................................ ................................ ............................. 26
p9242 - r datasheet ? 2016 integrated device technology, inc 5 december 16, 2016 1. pin a ssignments figure 1 . pin a ssignments 1 2 3 4 5 6 7 8 9 1 0 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 e p ( c e n t e r e x p o s e d p a d ) g n d p r e g v i n s w _ s g n d l d o 3 3 v i n _ l d o l d o 1 8 l e d 1 d - d + s c l s d a i l i m l e d _ p a t v c o i l t s b u z r o v p _ c t l s w _ b r g 1 g l _ b r g 1 g n d g l _ b r g 2 s w _ b r g 2 b s t _ b r g 2 g h _ b r g 2 g p i o r s v r s v c s p c s n i s n s _ o u t i d e m i v d e m 1 v b r g _ i n d r v _ v i n 1 1 1 2 l e d 2 v d d i o 2 6 2 5 r s v r s v 2 3 2 4 3 8 3 7 q _ d r v 1 q _ d r v 2 g h _ b r g 1 b s t _ b r g 1 r s v r s v e n g n d
p9242 - r datasheet ? 2016 integrated device technology, inc 6 december 16, 2016 2. pin descriptions table 1 . pin descriptions pins name type function 1 en i nput active - low enable pin . when connected to logic high , the p9242 - r enters the shut d own mode, which has a typical current consumption of 25 a . when connected to logic low , the device is in normal operation. 2, 6, 34, 41, ep gnd C ground connection. 3 preg o utput regulated 5v output used for internal device biasing . connect a 1 f capacitor from this pin to ground . this pin must not be externally loaded. 4 vin input input power supply . connect a 10f capacitor from this pin to ground. 5 sw_s output step - down regulator `s switch node . connect one of the terminals of the 4.7 h inductor to this pin. 7 ldo 33 output regulated 3.3 v output used for internal device biasing . connect a 1f capacitor from this pin to ground . this pin should not be externally loaded. 8 vin_ldo input linear regulator input power supply . connected this pin to the 5v output of the step - down regulator. 9 ldo 18 output regulated 1.8 v output used for internal device biasing . connect a 1 f capacitor from this pin to ground . this pin should not be externally loaded. 10 led1 input open - drain output . connect an led to this pin 11 led2 open - drain output . connect an led to this pin. 12 vddio input input power supply for internal biasing . this pin must be connected to ldo 33. 13 d - input logic i/o for usb travel adaptor detection . 14 d + input logic i/o for usb travel adaptor detection . 15 scl input i 2 c interface clock input . connect a 5.1k? pull - up resistor to ldo 33 rail . 16 sda i/o i 2 c interface data input and data output, connect a 5.1k ? pull - up resistor to ldo 33 rail . 17 ilim input programmable over - current limit pin. connect the center tap of the resistor divider to this pin to set the current - limit threshold. for more information, see section 7.1 . 18 led_pat input programmable led pattern selection. connect the center tap of the resistor divider to this pin. for more information on various led blinking pattern s , see section 7.8 . 19 vcoil input i nput for coil voltage sensing. 20 ts input remote temperature sensor for over - temperature shutdown. connect to the ntc thermistor network. if not used, connect to the ldo33 pin through the 10k resistor. 21 buz r output buzzer output . connect a buzzer to this pin. 22 ovp_ctl i/o logic high during power transfer phase used to s cale down the voltage to detect over - voltage for vcoil pin . 23 q_drv1 i/o control signal for q factor measurement circuit. 24 q_drv2 i/o control signal for q factor measurement circuit.
p9242 - r datasheet ? 2016 integrated device technology, inc 7 december 16, 2016 pins name type function 25, 26 , 27, 28 , 42, 43 rsv output reserved for internal use. do not connect. 29 gpio i/o general purpose digital i/o pin. 30 gh_brg2 output gate driver output for the high - side fet of half bridge 2 . connect this pin to a series 12
p9242 - r datasheet ? 2016 integrated device technology, inc 8 december 16, 2016 3. absolute maximum ratings the absolute maximum ratings are stress ratings only. stresses beyond those listed under absolute maximum ratings m ight cause permanent damage to the p9242 - r . functional operation of the p9242 - r at absolute maximum ratings is not implied. exposure to absolute maximum rating conditions for extended periods could affect long - term reliability. table 2 . absolute maximum ratings pin s [a] ratin g [b] units en ? ? ? ? , vin, sw_s, vbrg_in, sw_brg1, sw_brg2, csp, csn, bst_brg1, bst_brg2, gh_brg1, gh_brg2 - 0.3 to 28 v preg, ldo33 , v in _ldo , led1, led2, vddio, scl, sda, ilim , led_pat, vcoil, t s , buzr, ovp_ctl , gpio , d - , d+, q_drv1 , q_drv2 , gl_brg1 , gl_brg2, vdem1, idem i , isns_out, drv_vin - 0.3 to 6 v ldo18 - 0.3 to 2 v [a] a bsolute maximum ratings are not provided for reserved pins (rsv). these pins are not used in the application. [b] all voltages are referred to ground unless otherwise noted. all gnd pins and the exposed pad (ep) connected together. table 3 . package thermal information symbol description vfqfn rating units ? ja thermal resistance junction to ambien t [a] , [b] , [c] 27.2 ? c/w ? jc thermal resistance junction to cas e [b] , [c] 18.8 ? c/w ? jb thermal resistance junction to boar d [b] , [c] 1.36 ? c/w t j operating junction temperatur e [a] , [b] - 40 to +125 ? c t a ambient operating temperatur e [a] , [b] - 40 to +85 ? c t stg storage temperature - 55 to +150 ? c t lead lead temperature (soldering, 10s ) +300 ? c [a] the maximum power dissipation is p d(max) = (t j(max) - t a ) / ja where t j(max) is 125c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. [b] this thermal rating was calculated on a jedec 51 - standard 4 - layer board with the dimensions 76.2 x 114.3 mm i n still air conditions. [c] actual thermal resistance is affected by pcb size, solder joint quality, layer count, copper thickness, air flow, altitude, a nd other unlisted variables. table 4 . esd information test model pins ratings units hbm all pins. 2000 v cdm all pins. 500 v
p9242 - r datasheet ? 2016 integrated device technology, inc 9 december 16, 2016 4. electric al characteristics table 5 . electrical characteristics note: v in = 5 v, en ? ? ? ? = low , t a = - 4 0 ? c to +85 ? c, unless otherwise noted. typical values are at 25 ? c . symbol description conditions/notes min typical max units input supplies and uvlo v in input operating range [a] 4.25 21 v v in_uvlo under - voltage lockout v in r ising 4.0 v v in_uvhys under - voltage hysteresis v in f alling 0.5 v i in operating mode input current power transfer phase , vin = 12v 10 ma i std_by standby mode current periodic ping 1 ma i shd shut down current en ? ? ? ? = v in = 21v 25 80 a enable pin threshold ( en ? ? ? ? v ih input threshold high 2.5 v v il input threshold l ow 0.5 v i en_lkg en ? ? ? ? pin input leakage current v en = 0v - 1 1 a v en = 5v 2.5 a step - down r egulato r [b] with c out = 33f; l = 4.7h v out step - down output voltage vin = 12v 4.5 5 5.5 v n - channel mosfet drivers t ls_on_off low - side gate driver rise and fall t imes c l oad = 3nf; 10 % to 90%, 90% to 10% 50 150 ns t hs_on_off high - side gate driver rise and fall t imes c l oad = 3nf; 10 % to 90%, 90 % to 10% 150 300 ns input current sense v sen_ofst amplifier output offset voltage measured at the isns_out pin; v csp = v csn 0.6 v isen acc_ty p [c] measured current sense accuracy v r_isen = 25mv , i = 1.25a 3.5 % analog to digital converter n resolution 12 bit channel number of channels 10 v in,fs full scale input voltage 2.4 v
p9242 - r datasheet ? 2016 integrated device technology, inc 10 december 16, 2016 symbol description conditions/notes min typical max units ldo1 8 [b] v ldo 18 1.8v ldo regulator c out = 1f , v vi n_ldo = 5.5 v 1.71 1.8 1.89 v ldo3 3 [b] v ldo 33 3.3v ldo regulator c out = 1f , v vi n_ldo = 5.5 v 3.15 3.3 3.45 v preg v preg 5v ldo regulator 5 v thermal shutdown t sd thermal shutdown threshold r ising 140 c threshold f alling 120 c analog input pins input current leakage (t s , vcoil) i lkg leakage current - 1 1 a open - drain p ins output logic levels (led1, led2, scl, sda) v oh output logic high 4 v v ol output logic l ow i = 8ma 0.5 v digital input/ o utput pins logic levels v ih input voltage high level 0.7 ? il input voltage low level 0.3 ? lkg leakage current 1 a v oh output logic high i = 8ma , vddio = 3.3v 2.4 v v ol output logic low i = 8ma , vddio = 3.3v 0.5 v i 2 c interface (scl, sda) f scl_slv clock frequency as i 2 c slave 400 khz c b capacitive load for each bus line 100 pf c bin scl, sda input capacitance 5 pf i lkg input leakage current v = gnd and 3.3v - 1 1 a [a] the input voltage operating range is dependent upon the type of transmitter power stage (full - bridge, half - bridge) and transmitting coil inductance. wpc sp ecifications should be consulted for appropri ate input voltage ranges by end - product type. [b] do not externally load. for i nternal biasin g only. [c] a 20m, 1% or better sense resistor and a 4.7, 1% input filter resistor are required to meet the fod specification.
p9242 - r datasheet ? 2016 integrated device technology, inc 11 december 16, 2016 5. typical performance characteristics v in = 12.0 v; en ? ? ? ? = low . t he following p erformance characteristics were taken using a p9221 - r , 15 w wireless power receiver (r x ) at t a = +25 ? c unless otherwise noted. figure 2 . efficiency vs. output load: v out _rx = 12v figure 3 . efficiency vs. output load: v out _rx = 9v figure 4 . efficiency vs. output load: v out _rx = 5v figure 5 . load r eg ulation vs. output load: vcc_5v in schematic figure 24 figure 6 . load reg ulation vs. output load: ldo33 figure 7 . load reg ulation vs. output load: ldo18 50 55 60 65 70 75 80 85 90 0.1 0.3 0.5 0.7 0.9 1.1 1.3 efficiency [%] output current[a] 40 45 50 55 60 65 70 75 80 85 90 0.1 0.3 0.5 0.7 0.9 1.1 1.3 efficiency [%] output current [a] 40 45 50 55 60 65 70 75 80 85 90 0.1 0.3 0.5 0.7 0.9 1.1 efficiency [%] output current [a] 4.9 5 5.1 5.2 5.3 0 10 20 30 40 50 60 70 80 vcc_5v [v] output current[ma] vcc_5v @85 c vcc_5v @25 c vcc_5v @0 c vcc_5v @-40c 3.2 3.25 3.3 3.35 3.4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 lod33 [v] output current[ma] ldo33 @85 c ldo33 @25 c ldo33 @0 c ldo33 @-40 c 1.7 1.75 1.8 1.85 1.9 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ldo18 [v] output current[ma] lod18 @85 c lod18 @25 c lod18 @0c lod18 @-40 c
p9242 - r datasheet ? 2016 integrated device technology, inc 12 december 16, 2016 figure 8 . over - current limit vs. v ilim figure 9 . voltage and current signal for demodulation figure 10 . enable startup figure 11 . communication packet during r x load step from 0 to 1.3a figure 12 . communication packet during r x load step from 1.3a to 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 over current proection[ma] v ilim [v]
p9242 - r datasheet ? 2016 integrated device technology, inc 13 december 16, 2016 6. function block diagram figure 13 . function al block diagram h a l f b r i d g e d r i v e r s c o n t r o l 3 2 - b i t a r m p r o c e s s o r s c l s d a b s t _ b r g 1 g h _ b r g 1 s w _ b r g 1 g l _ b r g 1 h a l f b r i d g e d r i v e r s c o n t r o l b s t _ b r g 2 g h _ b r g 2 s w _ b r g 2 g l _ b r g 2 p w m g e n e r a t o r a n d f s k m o d u l a t o r c s n c s p + - + - i s n s _ o u t i d e m i v d e m 1 a s k d e c o d e r v b r g _ i n d r v _ v i n i s n s d a t a o t p d a t a s r a m i 2 c v i n 5 v b u c k l d o 3 3 p r e g l d o 1 8 l d o 5 v s w _ s v i n _ l d o l d o 3 3 l d o 1 8 5 v 3 . 3 v 1 . 8 v d + d - u s b d e t e c t g n d e n l e d 1 l e d 2 o s c t s i l i m l e d _ p a t v c o i l b u z r g n d 1 2 m u x o v p _ c t l q _ d r v 1 q _ d r v 2 g p i o e p v d d i o i / o m o d u l e i s n s v i n a d c r s v
p9242 - r datasheet ? 2016 integrated device technology, inc 14 december 16, 2016 7. theory of operation a wireless power charging system has a base station with one or more transmitters that make power available via dc - to - ac inverter(s) and transmit the power over a strongly - coupled inductor pair to a receiver in a mobile device. the amou nt of power transferred to the mobile device is controlled by the wireless power receiver by sending communication packets to the transmitter to increase, decrease , or maintain the power level. the communication from receiver t o transmitter is purely digit al and consist s of 1s and 0s that ride on top of the power link that exists between the transmitter (tx) and receiver (rx) coil. communication from transmitter to receiver is achieved by frequency shift keying ( fsk ) modulation over the power signal frequency and amplitude shift keying (ask) is used for the communication protocol from receiver to transmitter. a feature of the wireless charging system is the fact that when it is not delivering power , the transmitter is in s tandby m ode . the transmitte r remains in standby m ode and periodically pings until it detects the presence of a receiver . once an extended power profile r eceiver is detected , such as the p9221 - r or equivalent , the transmi tter will provide with up to 15 w of output power. if a baseline power profile rec eiver is present, the trans mitter will deliver only up to 5 w of output power. the p9242 - r contains features that ensure a high level of functionality and compliance with the wpc requirement s , such as a pow er path that efficiently achieves power transfer, a simple and robust communication demodulation circuit, safety and protection circuits, configuration , and status indication circuits . 7.1 over - current limit C ilim the over - current protection (ocp) is designed to protect the half - bridge and wireless receiver unit from becoming exposed to operating conditions that could potentially cause damage or unexpected behavior from the system. the input current is continuously moni tored during the power transf er stage. if the input current goes above the ocp threshold of 2.1a (typical) , the p9242 - r will increase the switching frequency or reduce the duty cycle in order to keep the input current below the ocp value. 7.2 enable pin C en ? ? ? ? ? the p9242 - r can be disabled b y applyi ng a logic high to the en pin. when the voltage on the en pin is pulled high, operation is suspended and the p9242 - r is placed in the low - current s hut down mode . if pulled low, the p9242 - r is active. 7.3 buzzer C buz r an optional ac - type ceramic buzzer can be connected between the buz r pin to gnd through a current limiting resistor. a short 4 k hz chirp sound will indicate when the object is detected. do not connect this pin if the b uzzer function is not desired . 7.4 voltage demodulation C vdem1 in order to increase the communication re liability in any load condition , the p9242 - r has integrated two demodulation schemes, one based on coil current information and the other based on coil voltage modulation. the voltage mode envelope detector is implemented us in g a discrete solution as depicted on figure 14 . this simple implementation achieves the envelope detector function low - pass filter as well as the dc f ilter function. figure 14 . voltage mode envelope detector d 1 r 1 r 2 c 1 r 3 c 2 c 3 p a c k e t d e c o d e r t o r e g i s t e r s p 9 2 4 2 - r v d e m 1
p9242 - r datasheet ? 2016 integrated device technology, inc 15 december 16, 2016 7.5 current demodulation C idem i the current - mode detector takes the modulation information from the current sense resistor , which carries the coil current modulation information in addition to the averaged input current . ther e is an additional discrete low - pass filter and dc filter between the isns_out and idemi pins. the packet decoder block is shared between the voltage - mode and current - mode detectors. the packet decoder selects either voltage - mode or current - mode signals depending upon which produces the best demodulated signal. figure 15 . current mode envelope detector 7.6 t hermal p rotec tion the p9242 - r integrates thermal shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. this circuitry will shut down or reset the p9242 - r if the die temperature exceeds a threshold t o prevent damage resulting from excessive thermal stress that m ight be encountered under fault conditions . a n internal temperature protection block is enabled in the p9242 - r that monitors the temperature inside the chip. if the die temperature exceeds 140c , the chip shuts down and resume s when the internal temperature drops below 120c. 7.7 external temperature sensing C ts the p9242 - r has a temperature sensor input, ts, which can be used to monitor an external temperature by using a thermistor. the built - in comparators reference voltage was chosen to be 0.6v in the p9242 - r, and it is used for monitoring the voltage level on the ts pin . figure 16 . ntc thermistor connection to ts pin t o disable the the rmistor, the ts pin should be connected to the ldo33 pin . do not leave the ts pin floating. 7.8 leds p attern s election C led_pat the p9242 - r uses two leds to indicate the power transfer status, faults and operating modes. leds are connected to led1 and led2 pins as shown on the typical application schematic figure 24 . the led pattern s can be programmed by setting the voltage on the led_pat pin through the resistor divider r 43 and r 44 as shown on figure 24 . c s p c s n v i n v b r i d g e i s n s _ o u t i d e m i p a c k e t d e c o d e r t o r e g i s t e r s 2 0 m p 9 2 4 2 - r r 1 c 1 c 2 c 3 c 1 l d o 3 3 t s p 9 2 4 2 - r a d c
p9242 - r datasheet ? 2016 integrated device technology, inc 16 december 16, 2016 table 6 . led pattern selection option voltage on led_pat p in led1/led2 p in status standby transfer complete fault 1 pull - down or 0.075v led1 C green off on off off led2 C red off off off blink 4hz 2 0.225 v led1 C green on on off off led2 C red on off off blink 4hz 3 0.375 v led1 C green off blink 1hz on blink 4hz led2 C red off off off off 4 0.525 v led1 C green off on off blink 4hz led2 C red off off off off 5 0.675 v led1 C green on blink 1hz on off led2 C red on off off blink 4hz 6 0.825 v led1 C green off off on off led2 C red off on off blink 4hz 7 0.975 v or pull - up led1 C green off blink 1hz on off led2 C red off off off blink 4hz 7.9 foreign o bject d etection when metallic objects, such as coins, keys, and paperclips, are exposed to alternating magnetic fields, the eddy current flow ing through the object will heat up. the amount of heat generated is a function of the amplitude and frequency of the magnetic fiel d, as well as the characteristics of the object , such as resistivity, size, and shape. in any wireless power system, the heat generated by the eddy current manifests itself as a power loss reducing the overall system efficiency. if appropriate measures are not taken, the heating could lead to unsafe situation. in extended power profile, there are two stages of f oreign object detection (fod). one is by measuring the system quality factor prior to entering the power transfer phase, and the other is to measure the power loss difference between the received power and the transmit ted power during the power transfer phase. prior to entering the power transfer phase, the p9242 - r detects a change in the coils quality factor (q - factor) when a wireless power receiver or metal object has been placed on its surface. the transmitter measures the q - factor and compares it with the reference q - f actor provided by the receiver. if the difference is higher than the reference q - factor, the p9242 will identify it as fod and shut down the system. the second stage of the foreign object detection is during the power transfer where the power loss difference between the received power and transmitted power is constantly measured and c ompared to the wpc - 1.2.2 - specified threshold. if th e difference is higher than the threshold set by the wpc specification, the system will shut down to avoid over - heating.
p9242 - r datasheet ? 2016 integrated device technology, inc 17 december 16, 2016 7.10 step - d own regulator the input capacitors (c14 and c15 in figure 24 ) must be connected as close as possible between the vin pin and gnd pin. similarly, the output capacitor (c4 and c5 in figure 24 ) must be placed close to the inductor and gnd. the output voltage is sensed by the vin_ldo pin; therefore, the connection from the step - down output (vcc_5v; see figure 24 ) to the vin_ldo pin should be made as wide and short as possible to minimize output voltage errors. the step - down regulator is the input voltage to the ldo18 and ldo33 lin ear regulators and is not recommended for power ing an external load . 7.11 linear r egulators C preg, ldo33 , and ldo18 the p9242 has three low - dropout (ldo) regulators used to bias the internal circuitry. the 5v pre - regulator (preg) provides bias for the entire internal power management. the preg requires a 1f ceramic bypass capacitor connected from the preg pin to gnd. this capacitor must be plac ed very close to the preg pin. the voltage regulator must not be externally loaded. the ldo33 and ldo18 are used to b ias the internal digital circuit. the regulators input voltage is supplied thro ugh the vin_ldo pin. both regulators require a 1f ceramic capacitor from the pin to gnd. the voltage regulators must not be externally loaded . 7.12 under - v oltage lock - out (uvlo) p rotection the p9242 - r has 4v ( typical , rising) under - voltage lockout circuit on the vin pin. to guarantee proper functionality , the voltage on the vin pin must rise above the uvlo threshold. if the input voltage stays below the uvlo threshold, the p9242 - r is in shut down mode. figure 17 . uvlo threshold definition 7.13 lc resonant circuit the lc resonant circuit comprises the series primary resonant coil (l p ) and series capacitance (c p ). the transmitter coil assembly is vendor specific, and it must comply with the wpc recommendation. the wpc recommendations include the self - inductance value, dc resistance (dcr), q - factor, size, and number of turns. the p9242 - r is designed for an mp - a2 coil configuration using half - bridge and full - bridge inverter topologies to drive the primary coil (l p ) and a series capacitance (c p ). within the operating frequency range from 110khz to 145khz, the assembly of the primary coil and shielding has a self - inductance of l p = 10.0h 1 0%, and the value of the series capacitance is c p = 215nf 5%, according to the wpc specification. near resonance, the voltage developed across the c p series capacitance could reach 70v peak. high - voltage (100v) cog - type ceramic capacitors are highly recom mended for their ac and dc characteristics and temperature stability . the recommended parts are listed on the bill of materials (bom) in table 15 . s h u t d o w n m o d e s h u t d o w n m o d e n o r m a l o p e r a t i n g m o d e t i m e v i n _ u v h y s v i n _ u v l o v i n [ v ]
p9242 - r datasheet ? 2016 integrated device technology, inc 18 december 16, 2016 8. comm unication interface 8.1 modulation/communication the wpc - 1.2.2 extended power profile specification uses two - way communication for power transfer: receiver - to - transmitter and transmitter - to receiver. receiver - to - transmitter communication is accomplished by mod ulating the load seen by the receiver's coil ; the communication is purely digital and symbols 1s and 0s carried on the power signal. modulation is done with amplitude - shift keying (ask) modulation using with a bit - rate of 2kbps. to the transmitter, this appears as an impedance change, which results in measurable variations of the transmitters coil. the power transmitter demodulates this variation of the coil current or voltage to receive the packets. transmitter - t o - receiver communication is accomplished by frequency - shift keying (fsk) modulation over the power signal frequency. the power transmitter p92 42 - r has the means to modulate fsk data from the power signal frequency and use it in order to establish the hands haking protocol with the power receiver . the p92 42 - r implements fsk communication when used in conjunction with wpc - compliant receiver s, such as the p92 21 - r. the fsk communication protocol allows the transmitter to send data to the receiver using the power transfer link in the form of modulating the power transfer signal. this modulation appears in the form of a change in the base operating frequency (f op ) to the modulated operating frequency (f mod ) in periods of 256 consecutive cycles. equation 1 should be used to compute the modulated frequency based on any given operating frequency. communication packets are transmitted from transmitter to receiver w ith less than 1% positive frequency deviation following any receiver - to - transmitter communication packet. the frequency deviation is calculated using equation 1 . f mod = 60000 60000 f op ? 3 [ khz ] equation 1 where f mod is the chang e in frequency in the power signal frequency; f op is the base operating frequency of power transfer; and 60,000khz is the frequency of the internal oscillator responsible for counting the period of the power transfer signal. the fsk byte - encoding scheme and packet structure complies with the wpc specification revision 1.2.2. the fsk communication uses a bi - phase encoding scheme to modula te data bits into the power transfer signal. the start bit will consist of 512 consecutive f mod cycles (or logic 0). a logic 1 value will be sent by sending 256 consecutive f op cycles followed by 256 f mod cycles or vice versa, and a logic 0 is sent b y sending 512 consecutive f mod or f op cycles. figure 18 . example of differential bi - phase encoding for fsk each byte will comply with the start, data, parity, and stop asynchronous serial format structure shown in figure 19 : figure 19 . example of asynchronous serial byte format for fsk t c l k = 2 5 6 / f o p o n e z e r o o n e z e r o o n e o n e z e r o z e r o 5 1 2 c y c l e s 2 5 6 c y c l e s start stop parity b 0 1 2 3 4 5 6 7 b b b b b b b
p9242 - r datasheet ? 2016 integrated device technology, inc 19 december 16, 2016 8.2 bit de coding scheme for ask as required by the wpc, the p92 42 - r uses a differential bi - phase coding scheme to de modulate data bits onto the power signal. a clock frequency of 2khz is used for this purpose. a logic one bit is coded using two narrow transitions, whereas a logic zero bit is encoded using one w ider transition as shown below: figure 2 0 . bit de coding scheme 8.3 byte de coding for ask each byte in the communication packet comprises 11 bits in an asynchronous serial format, as shown in figure 21 . figure 21 . byte de coding scheme each byte has a start bit, 8 data bits, a parity bit, and a single stop bit. 8.4 packet structure the p92 42 - r communicates with the base station via communication packets. each commun ication packet has the following structure: figure 22 . communication packet structure preamble header message checksum t clk one zero one zero one one zero zero s t a r t s t o p p a r i t y b 0 1 2 3 4 5 6 7 b b b b b b b
p9242 - r datasheet ? 2016 integrated device technology, inc 20 december 16, 2016 9. wpc mode characteristics the wpc - 1.2.2 extended power profile wireless power specif ication has a negotiation phase, c alibration phase, and renegotiation phase, as shown in figure 23 . figure 23 . wpc power tran sfer phases flow c hart 9.1 selection phase in the selection phase, the power transmitter determines if it will proceed to the ping phase after detecting the placement o f an object. in this phase, the power transmitter typically monitors the interface surface for the placement and removal of objects using a small measurement signal. this measurement signal should not wake up a power receiver that is positioned on the interface surface. 9.2 ping phase (digital ping) in the ping phase, the power transmitter will transmit power and will detect the response from a possible power receiver. this response ensures the power transmitter that it is dealing with a power receiver rather than some unknown object. when a power receiver is placed on a wpc qi charging pad, it responds to the application of a power signal by rectifying this power signal. when the internal bias voltage is greater than a specific threshold level , then receiver is initiated enabling the wpc communication protocol. if the power transmitter correctly receives a signal strength packet, the power transmitter proceeds to the identification and configuration phase of the power transfer, maintaining the power signal output. s t a r t o b j e c t d e t e c t e d e r r o r c o n d i t i o n n e g o t i a t i o n f a i l u r e o r e r r o r c o n d i t i o n o r f o d c a l i b r a t i o n s u c c e s s f u l n e g o t i a t i o n s u c c e s s f u l n e g o t i a t i o n r e q u e s t e d n o n e g o t i a t i o n r e q u e s t e d ( < = 5 w p o w e r r e c e i v e d o n l y ) r e n e g o t i a t i o n c o m p l e t e d c a l i b r a t i o n f a i l u r e o r e r r o r c o n d i t i o n n o r e s p o n s e o r n o p o w e r n e e d e d s e l e c t i o n p i n g i d e n t i f i c a t i o n a n d c o n f i g u r a t i o n n e g o t i a t i o n r e n e g o t i a t i o n c a l i b r a t i o n p o w e r t r a n s f e r p o w e r r e c e i v e r p r e s e n t p o w e r t r a n s f e r c o m p l e t e o r e r r o r c o n d i t i o n r e n e g o t i a t i o n r e q u e s t e d e r r o r c o n d i t i o n
p9242 - r datasheet ? 2016 integrated device technology, inc 21 december 16, 2016 9.3 identification and configuration phase the identificat ion and configuration phase is the part of the protocol that the power transmitter executes in order to identify the power re ceiver and establish a default power transfer contract. this protocol extends the digital ping in order to enable the power receive r to communicate the relevant information. in this phase, the power transmitter identifies itself and receive s information for a default power transfer contract as follows : ? it r eceives the configuration packet . ? if the power transmitter does not ac knowledg e th e request ( does not transmit fs k modulation), the power receiver will assume 5w output power. 9.4 negotiation phase in the negotiation phase, the power receiver negotiates changes to the default power transfer contract. in addition, the powe r receiver veri fies that the power transmitter has not detected a foreign object. 9.5 calibration phase in the calibration phase, the power receiver provides information that the power transmitter can use to improve its ability t o detect foreign objects during power transfe r. 9.6 power transfer phase in this phase, the p9242 - r controls the power transfer by means of the following control data packets: ? control error packets ? received p ower packet (rpp, fod - related) ? end power transfer (ept) packet once the identification and configuration phase is completed, the transmitter initiates the power transfer mode. the receiver`s control circuit sends error packets to the transmitter to adjust the rectifier voltage to the level required to maximize the e fficiency of the linear regulator and to send to the transmitter the actual received power packet for foreign object detection (fod) to guarantee safe , efficient power transfer. in the event of an ept issued by the application, when the receiver sends ept packets , the transmitter terminates the power transfer .
p9242 - r datasheet ? 2016 integrated device technology, inc 22 december 16, 2016 10. functional registers the following list of tables is a comprehensive list of address locations, field names, available operations (r or rw), defau lt values , and functional descriptions of all internal ly accessible registers contained within the p9242 - r . the default i 2 c slave address is 61 hex . table 7 . state register address and bit s register field name r/w default function and description 6e0 hex system state r 0 0 hex 0 dec = s tartup 1 dec = i dle 2 dec = analog ping phase 4 dec = digital ping phase 5 dec = wpc identification 7 dec = wpc configuration 8 dec = power transfer initialization 9 dec = power transfer state 11 dec = remove power 12 dec = restart 13 dec = wpc negotiation table 8 . status register address and bit s register field name r/w default function and description 6e1 hex system status r 0 0 hex 0 dec = system n ormal 1 dec = fod alarm 2 dec = ept charge complete 4 dec = ept no r esponse 5 dec = ept internal fault 6 dec = over - temperature alarm 7 dec = over - current 9 dec = ept o ther rx fault 10 dec = negotiation fail table 9 . read register C coil current address and bit s register field name r/w default function and description 6e2 hex [7:0] coil_current [7:0] r - 8 lsb of c oil current value in ma. 6e3 hex [7:0] coil_current [15:8] r - 8 msb of c oil current value in ma .
p9242 - r datasheet ? 2016 integrated device technology, inc 23 december 16, 2016 table 10 . read register C coil voltage address and bit s register field name r/w default function and description 6e4 hex [7:0] coil_voltage [7:0] r - 8 lsb of c oil voltage value in mv . 6e5 hex [7:0] coil_voltage [15:8] r - 8 msb of c oil voltage value in mv . table 11 . read register C remote temperature sensing voltage sensing voltage = thermistor adc value[15:0] ? 2 . 4v 4095 address and bit s register field name r/w default function and description 6e8 hex [7:0] thermistor adc value [7:0] r - 8 lsb of thermistor adc value. 6e9 hex [7:0] thermistor adc value [15:8] r - 8 msb of thermistor adc value. table 12 . read register C operating frequency f op = 60 mhz fre_ cnt [15:0] address and bit s register field name r/w default function and description 6ea hex [7:0] fre_cnt [7:0] r - 8 lsb of operating frequency count . 6eb hex [7:0] frq_cnt [15:8] r - 8 msb of operating frequency count. table 13 . read register C operating duty cycle duty cycle = duty_cnt ? 50% 255 address and bit s register field name r/w default function and description 6ec hex [7:0] d uty_ c nt [7:0] r - 8 lsb of operating duty count . 6ed hex [7:0] duty_cnt [15:8] r - 8 msb o f operating duty count. table 14 . read register C full/half b ridge status address and bit s register field name r/w default function and description 6ee hex [7:0] full/ h alf bridge status [7:0] r - 0 = h alf bridge. "1" = f ull bridge.
p9242 - r datasheet ? 2016 integrated device technology, inc 24 december 16, 2016 11. application information 11.1 power dissipation and thermal requirements the p9242 - r is offered in a 48 - vfqfn package that has a maximum power dissipation capability of about 1.47w . t he maximum power dissipation of the package is determined by the number of thermal vias between the package and the printed circuit board (pcb) . the maximum power dissipation of the package is de fined by the dies specified maximum operating junction temperature, t j(max) of 125c. the junction temperature rises when the heat generated by the devices power dissipation flow is impeded by the package - to - pcb thermal resistance. the vfqfn package off ers a typical thermal resistance, junction to ambient ( ja ), of 27.2c/w when the pcb layout design is optimized as described in the p9242 - r layout g uide document . the techniques noted in the pcb layout section must be followed when designing the printed c ircuit board layout. attention to the placement of the p9242 - r and bridge fet packages in proximity to other heat - generating devices in a given application design should also be considered . the ambient temperature around the power ic will also have an effe ct on the thermal limits of an application . the main factors influencing ja (in the order of decreasing influence) are pcb char acteristics, die/package attached thermal pad size (vfqfn) and thermal vias , and the final system hardware construction . board d esigners should keep in mind that the package thermal metric ja is impacted by the characteristics of the pcb . changing the design or configuration of the pcb changes the overall thermal resistivity and the boards heat - sinking efficiency . three basic ap proaches for enhancing thermal performance are listed below: ? improving the power dissipation capability of the pcb design. ? improving the thermal coupling of the component to the pcb. ? introducing airflow into the system. first, the maximum power dissipation for a given situation should be calculated using equation 2 : p d(max) = ( t j(max) ? t a ) ja equation 2 where p d(max) = maximum power dissipation ja = package thermal resistance (c/w) t j(max) = maximum device junction temperature (c) t a = ambient temperature (c) the maximum recommended operating junction temperature (t j(max) ) for the p9242 - r is 125c. the thermal resistance of the 48 - pin vfqfn package (ndg48) is optimally ja =27.2c/w. operation is specified to a maximum steady - s tate ambient temperature (t a ) of 85c. therefore, the maximum recommended power dissipation is given by the following equation : p d(max) = (125c - 85c) / 27.2c/w ? 1.47 watt all the previously mentioned thermal resistances are the values found when the p9242 - r is mounted on a standard board of the dimensions and characteristics specified by the jedec 51 standard.
p9242 - r datasheet ? 2016 integrated device technology, inc 25 december 16, 2016 11.2 typical application schematic the typical application schematic provides a basic guideline to understand ing and build ing a functional medium - power wireless power transmitter type mp - a2 as described in the wpc spec ifications . other components, not shown on the typical application schematic, m ight be needed in order to comply w ith other requirements, such as emc or thermal specifications. figure 24 . p9242 - r typical application schematic enb scl io_b1 r23 10k debugg, for development only c4 0.1uf r10 390k r22 np vsns_in c28 22uf q7 2n7002 vlx2 ldo33 c12 1uf gnd gpio ldo33 d- r33 3 c16 1uf r13 10k ilim r26 100k c35 5.6nf c30 0.1uf r34 100k q_drv2 ldo18 io_a7 r39 0 q_drv1 led2 vcc_5v led1 2 1 ldo33 isns_h io_b5 this document contains information proprietary to integrated device technology, inc. (idt). use or disclosure without the written permission of an officer of idt is expressly forbidden c2 0.1uf ts c11 22nf r5 np io_b1 gndt1 ldo33 r6 10k c41 10uf q2 dmg7430lfg 5 4 1 6 7 8 2 3 u2 np cs# 1 do 2 wp# 3 gnd 4 di 5 clk 6 hld# 7 vcc 8 epad 9 r41 10k r1 1k vcoil sda r36 0.1 r19 np lx1 q8 2n7002 r44 np c29 0.1uf led_pat r42 10k c10 22nf vin1 lx2 io_b2 r11 200k r30 100k r31 100k r32 100k vin c34 0.1uf io_b2 d2 bav21w vbrg usb_id c6 1uf tx-coil assembly c44 4.7u ldo33 r25 12 isns_h gnd1 vin io_b8 r46 5.1k r29 12 gnd3 ldo33 c13 0.1uf c14 10uf c25 np d- r28 12 d1 bav21w io_b1 r24 np r40 np c9 56p gnd2 scl r18 0.02 c36 np ldo33 vcc_5v sw_brg2 c1 0.1uf j3 ac_adapter c31 10uf programming connector c7 56p isns_out c15 0.1uf c24 47nf buzr r38 0 vcoil io_b0 led_pat c22 22nf j4 r14 2.4k io_a1 q1 dmg7430lfg 5 4 1 6 7 8 2 3 r21 10 q_drv2 io_b3 q6 sia453edj-t1-ge3 1 2 3 4 7 5 6 8 sda c8 6.8nf c43 1uf c23 68nf sda r43 10k io_b3 io_b0 c19 5.6nf c42 0.1uf r8 100k red r12 390k io_b0 io_a6 r3 1k io_b6 v s3 r48 10k gnd4 r9 100 gndt2 led2 2 1 c20 100nf q4 dmg7430lfg 5 4 1 6 7 8 2 3 io_b3 d+ c3 0.1uf ovp_ctl vlx1 r45 220 vint1 c27 1uf title size document number rev date: sheet of 2.1 p9242-r mm board v 2.1 custom 1 1 monday , december 12, 2016 q3 dmg7430lfg 5 4 1 6 7 8 2 3 ldo33 v_bridge c40 10uf v s2 io_a5 ldo33 t rth1 r15 10 ilim led_pat l2 np 1 2 3 4 c17 680p ilim ovp_ctl vint2 isns_in c32 22uf isns_l ldo33 sld sld vcc d- d+ id gnd j1 usb_micro_ab 1 2 3 4 5 6 7 8 9 10 11 pz1 buzzer 1 1 2 2 r47 5.1k vcc5v r16 10k c37 10uf io_b4 c18 1nf p9242-r u1 en 1 gnd 2 preg 3 vin 4 sw_s 5 gnd 6 ldo33 7 vin_ldo 8 ldo18 9 led1 10 led2 11 vddio 12 rsv 25 rsv 26 rsv 27 rsv 28 gpio 29 gh_brg2 30 bst_brg2 31 sw_brg2 32 gl_brg2 33 gnd 34 gl_brg1 35 sw_brg1 36 ep 49 bst_ brg1 37 gh_brg1 38 drv_vin 39 vbrg_in 40 gnd 41 42 rsv rsv 43 vdem1 44 idemi 45 isns_out 46 csn 47 csp 48 d- 13 d+ 14 scl 15 sda 16 ilim 17 led_pat 18 vcoil 19 ts 20 buzr 21 ovp_ctl 22 q_drv1 23 q_drv2 24 c33 0.1uf q_drv1 c38 10uf ldo33 io_a4 r37 0.1 ldo33 c39 5.6nf r27 12 ldo18 isns_l vcoil j2 68000-105hlf 1 1 2 2 3 3 4 4 5 5 r7 1k io_b2 j5 1 1 2 2 3 3 4 4 vin io_a0 gpio d+ vin q5 2n7002 green r20 10k r4 680 io_b7 r35 200k c21 0.1uf led1 c5 10uf c26 0.1uf scl l1 4.7uh
p9242 - r datasheet ? 2016 integrated device technology, inc 26 december 16, 2016 11.3 bill of materials (bom) table 15 . p9242 - r mm evaluation kit v2.1 bill of materials item reference quantity value description part number pcb footprint 1 c1 , c2 , c3 , c4 , c13 , c15 , c21 , c26 , c29 , c30 , c33 , c34 12 0.1uf cap cer 0.1uf 25v 10% x7r 0402 c1005x7r1e104k050bb 402 2 c5 , c14 , c31 , c37 , c38 , c40 , c41 7 10uf cap cer 10uf 25v 20% x5r 0603 c1608x5r1e106m080ac 603 3 c6 , c12 , c16 , c27 4 1uf cap cer 1uf 25v 20% x5r 0402 c1005x5r1e105m050bc 402 4 c7 , c9 2 56p cap cer 56pf 50v np0 0402 cl05c560jb5nnnc 402 5 c8 1 6.8nf cap cer 6800pf 25v x7r 0402 grm155r71e682ka01d 402 6 c10 , c11 2 22nf 0.022f 50v ceramic capacitor x7r 0603 gcm188r71h223ka37d 603 7 c17 1 680p cap cer 680pf 50v x7r 0402 cl05b681kb5nnnc 402 8 c18 1 1nf cap cer 1000pf 10% 50v x7r 0402 grm155r71h102ka01d 402 9 c19 , c35 , c39 3 5.6nf 5600pf 100v ceramic capacitor c0g, np0 0603 c1608c0g2a562j080ac 603 10 c20 1 100nf cap cer 0.1uf 100v c0g 1206 c3216c0g2a104k160ac 1206 11 c22 1 22nf cap cer 0.022uf 50v 10% x7r 0402 grm155r71h223ka12d 402 12 c23 1 68nf cap cer 0.068uf 100v np0 1206 c3216c0g2a683k160ac 1206 13 c24 1 47nf cap cer 0.047uf 100v np0 1206 c3216c0g2a473j115ac 1206 14 c25 1 np cap cer 10000pf 100v c0g 1206 c3216c0g2a103j115aa 1206 15 c28 , c32 2 22uf cap cer 22uf 25v 20% x5r 1206 grm31cr61e226ke15l 1206 16 c36 1 np cap cer 0.1uf 25v 10% x7r 0402 c1005x7r1e104k050bb 402 17 c42 1 0.1uf 0.10f 50v ceramic capacitor x7r 0603 grm188r71h104ka93d 603 18 c43 1 1uf 1f 25v ceramic capacitor x5r 0603 grm188r61e105ka12d 603 19 c44 1 4.7u 4.7f 25v ceramic capacitor x5r 0603 grm188r61e475ke11d 603 20 d1 , d2 2 bav21w diode gen purp 80v 125ma dfn bav21w - 7 - f sod123 21 vlx1 , vint1 , io_b1 , io_a1 , gndt1 , vs2 , vlx2 , vint2 , io_b2 , gndt2 , vs3 , io_b3 , io_b4 , io_a4 , vcc5v , io_b5 , io_a5 , io_b6 , io_a6 , io_b7 , io_a7 , io_b8 , ldo18 , ldo33 , vsns_in , vcoil , vbrg , io_b0 , io_a0 , enb 30 pth_tp 30 gauge wire pad np test_pt30dpad 22 vin1 , gnd1 , gnd2 , gnd3 , gnd4 , vin , gnd 7 tp test point pc miniature smt 5015 test_pt_sm_135x70 23 j1 1 5p conn rcpt mcr usb ab smd th shll zx62d - ab - 5p8 usb_micro_ab 24 j2 1 68000 - 105hlf bergstik ii .100" sr straight 68000 - 105hlf sip5 25 j3 1 ac_adapter conn power jack 2.5x5.5mm hi cur pj - 002ah conn_power_jack5 _5mm
p9242 - r datasheet ? 2016 integrated device technology, inc 27 december 16, 2016 item reference quantity value description part number pcb footprint 26 j4 1 tp conn header 3pos .100" str gold 901200763 sip3 27 j5 1 sip con 4 positions header, unshrouded connector 0.100" (2.54mm) through hole gold or gold, gxt? 961104 - 6404 - ar sip - 4 28 led1 1 led led red clear 0603 smd 150060rs75000 0603_diode 29 led2 1 led led green clear 0603 smd 150060gs75000 0603_diode 30 lx1 , lx2 2 np tx coil assemble through hole na tp_txcoil 31 l1 1 4.7uh fixed ind 4.7uh 620ma 500 mohm cig10w4r7mnc l0603 32 l2 1 np common mode emi choke acm4520 - 901 - 2p - t - 000 emi_tdk_acm4520l 33 pz1 1 buzzer buzzer piezo 4khz 12.2mm pc mnt ps1240p02ct3 9235_buzzer 34 q1 , q2 , q3 , q4 4 dmg7430lf g mosfet n - ch 30v 10.5a pwrdi3333 dmg7430lfg - 7 powerdi3333_8ld_fet 35 q5 , q7 , q8 3 2n7002 n - channel 60 - v (d - s) mosfet 2n7002kt1g sot23_3 36 q6 1 sia453edj - t1 - ge3 mosfet p - ch 30v 24a ppak sc - 70 - 6 sia453edj - t1 - ge3 sc70_6ld_fet 37 rth1 1 np ntc thermistor 10k bead ntcle203e3103jb0 805 38 r1 , r3 , r7 3 1k res smd 1k ohm 5% 1/16w 0402 rc0402jr - 071kl 402 39 r4 1 680 res smd 680 ohm 5% 1/16w 0402 rc0402jr - 07680rl 402 40 r5 1 np res smd 0.0 ohm jumper 1/10w rc0402jr - 070rl 402 41 r6 , r13 , , r16 , r20 , r23 , r41 , r42 , r43 , r48 9 10k res smd 10k ohm 1% 1/10w 0402 rc0402fr - 0710kl 402 42 r8 , r26 , r30 , r31 , r32 5 100k res smd 100k ohm 5% 1/10w 0402 erj - 2gej104x 402 43 r24 1 np res smd 100k ohm 5% 1/10w 0402 erj - 2gej104x 402 44 r9 1 100 res smd 100 ohm 5% 1/10w 0603 rc0603jr - 07100rl 603 45 r10 , r12 2 390k res smd 390k ohm 5% 1/10w 0603 erj - 3geyj394v 603 46 r14 1 2.4k res smd 2.4k ohm 5% 1/10w 0402 erj - 2gej242x 402 47 r11 , r35 2 200k res smd 200k ohm 1% 1/10w 0603 rc1608f204cs 603 48 r15 , r21 2 10 res smd 10 ohm 1% 1/10w 0402 erj - 2rkf10r0x 402 49 r18 1 0.02 res smd 0.02 ohm 1% 1/8w 0805 wsl0805r0200fea 805 50 r19 , r22 , r40 , r44 4 np res smd 10k ohm 1% 1/10w 0402 rc0402fr - 0710kl 402 51 r25 , r27 , r28 , r29 4 12 res smd 12 ohm 5% 1/10w 0402 erj - 2gej120x 402 52 r33 1 3 res smd 3 ohm 1% 1/8w 0805 rc0805fr - 073rl 805 53 r34 1 100k res smd 100k ohm 1% 1/10w 0603 erj - 3ekf1003v 603 54 r36 , r37 2 0.1 res smd 0.1 ohm 5% 1/6w 0402 erj - 2bsjr10x 402 55 r38 , r39 2 0 res smd 0.0 ohm jumper 1/10w rc0402jr - 070rl 402 56 r45 1 220 res smd 220 ohm 1% 0.4w 0805 rc1206fr - 07220rl 1206 57 r46 , r47 2 5.1k res smd 5.1k ohm 5% 1/16w 0402 mcr01mrtj512 402 58 u1 1 p9242 - r medium power transmitter p9242 - r socketqfn_48_6x6_0p4 59 u2 1 np spiflash 2m - bit 4kb uniform sect w25x20cluxig tr uson_2x3_8ld
p9242 - r datasheet ? 2016 integrated device technology, inc 28 december 16, 2016 12. package outline drawing figure 25 . 48 - vfqfn package outline drawing
p9242 - r datasheet ? 2016 integrated device technology, inc 29 december 16, 2016 13. recommended land pattern figure 26 . 48 - vfqfn land pattern drawing
p9242 - r datasheet ? 2016 integrated device technology, inc 30 december 16, 2016 14. special notes: ndg 48 - vfqfn package assembly unopened dry packaged parts have a one - year shelf life. the hic indicator card for newly - opened dry packaged parts should be checked. if there is any moisture content, the parts must be baked for a minimum of 8 hours at 125?c within 24 hours prior to the assembly reflow process . 15. marking diagram 1. line 1 : c ompany name and part number . 2. line 2: - r is part of the part number , which is followed by the package code . 3. line 3: y y ww is the last two digit s of the year and two digits for the week that the part was assembled. # is the device step .$ denotes the mark code . 16. ordering information orderable part number description and package msl rating shipping package ambient temperature p9242 - rndgi8 p9242 - r wireless power receiver for 15w applications, 48 - vfqfn ( 6 x 6 mm ) package (ndg48) msl1 tape and reel 0c to +85c
p9242 - r datasheet ? 2016 integrated device technology, inc 31 december 16, 2016 17. revision history revision date description of change december 1 6 , 2016 initial release. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 284 - 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of user s. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. fo r datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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